library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity pwm_generator_tb is
end entity pwm_generator_tb;

architecture structural of pwm_generator_tb is

  component pwm_generator is
	 port (	clk		: in	std_logic;
		  reset		: in	std_logic;
		  direction	: in	std_logic;
		  count_in	: in	std_logic_vector (19 downto 0);
		
		

		  pwm		: out	std_logic
	 );
	 end component pwm_generator;

	signal	clk			: std_logic;
	signal	reset			: std_logic;
	signal	direction		: std_logic;
	signal pwm_test : std_logic;
	signal count_in :  std_logic_vector (19 downto 0);
	
begin


lbl0:	pwm_generator	port map (	clk		=> clk,
					reset		=> reset,
					direction => direction,
					count_in	=> count_in,
					pwm => pwm_test
			);
			
			
			


lbl1: clk		<= 	'0' after 0 ns,
		   		'1' after 10 ns when clk /= '1' else
				'0' after 10 ns;
lbl2: reset <= '1' after 0 ns,
	             '0' after 80 ns when reset /= '0' else
	             '1' after 80 ns;
direction <= '1' after 0 ns,
	             '0' after 160 ns when direction /= '0' else
	             '1' after 160 ns;

count_in <= std_logic_vector(to_unsigned(0,20)) after 0 ns,
            std_logic_vector(to_unsigned(1,20)) after 20 ns,
            std_logic_vector(to_unsigned(0,20)) after 320 ns,
            std_logic_vector(to_unsigned(1,20)) after 340 ns,
            std_logic_vector(to_unsigned(5e4,20)) after 360 ns,
            std_logic_vector(to_unsigned(0,20)) after 640 ns,
            std_logic_vector(to_unsigned(1,20)) after 660 ns,
            std_logic_vector(to_unsigned(1e5,20)) after 680 ns,
            std_logic_vector(to_unsigned(0,20)) after 960 ns,
            std_logic_vector(to_unsigned(1,20)) after 980 ns,
            std_logic_vector(to_unsigned(0,20)) after 1000 ns;
            

	 --pwm_test <= '1' after 0 ns;
end architecture structural;


